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AV4 VL-BUS MAIN BOARD
ABIT COMPUTER CORPORATION

AV4 VL-BUS MAIN BOARD

USER CONFIGURABLE SETTINGS
Function		Jumper	Position
�	VESA bus speed select 20/25/33MHz	JP8 and JP10	pins 1 & 2 closed
	VESA bus speed select 50MHz	JP8 and JP10	pins 2 & 3 closed
�	VESA bus wait state select 1	JP9 and JP11	pins 1 & 2 closed
	VESA bus wait states select 0	JP9 and JP11	pins 2 & 3 closed
�	CMOS memory normal operation	JP12	pins 1 & 2 closed
	CMOS memory clear	JP12	pins 2 & 3 closed
�	Fast gate A20 select enabled	JP17	pins 1 & 2 closed
	Fast gate A20 select disabled	JP17	pins 2 & 3 closed
�	Monitor type select color	JP18	closed
	Monitor type select monochrome	JP18	open
�	Factory configured - do not alter 1	JP23	See note
�	Factory configured - do not alter 1	JP24	See note
�	Factory configured - do not alter 1	JP25	See note
�	Factory configured - do not alter 1	JP26	pins 2 & 3 closed
�	Factory configured - do not alter	JP27	pins 2 & 3 closed
�	Factory configured - do not alter 1	JP28	See note
Note:The locations of JP23, JP24, and JP25 are unknown Note 1 :JP23 through JP28 are set at the factory depending on whether the R1 or R2 Model is shipped.

SRAM CONFIGURATION
Size	Cache SRAM	Location	TAG(U14)	TAG(U15)
64KB	(8) 8K x 8	Banks 0 & 1	(1) 8K x 8	(1) 8K x 8
128KB	(4) 32K x 8	Bank 0	(1) 8K x 8	(1) 8K x 8
256KB	(8) 32K x 8	Banks 0 & 1	(1) 32K x 8	(1) 32K x 8
Note:If SRAM is installed at U15 then write-back caching is enabled. If SRAM is installed at U14 and U15 then write-back or write-through caching can be enabled.