INFORMTECH INTERNATIONAL, INC.
BABY 286LJ VER. 1.0
|
Processor |
80286 |
|
Processor Speed |
12/16MHz |
|
Chip Set |
Headland |
|
Max. Onboard DRAM |
4MB |
|
Cache |
None |
|
BIOS |
Phoenix |
|
Dimensions |
220mm x 218mm |
|
I/O Options |
None |
|
NPU Options |
80287 |
|
CONNECTIONS | |||
|
Purpose |
Location |
Purpose |
Location |
|
Keyboard connector |
JP1 |
Turbo switch |
JP10 |
|
External battery |
JP2 |
Reset switch |
JP11 |
|
Speaker |
JP8 |
Power LED & keylock |
JP12 |
|
Turbo LED |
JP9 | ||
|
USER CONFIGURABLE SETTINGS | |||
|
Function |
Jumper |
Position | |
|
|
On board parity check enabled |
JP3 |
Open |
|
On board parity check disabled |
JP3 |
Closed | |
|
|
CMOS memory normal operation |
JP4 |
Open |
|
CMOS memory clear |
JP4 |
Closed | |
|
|
BIOS type select 27128 |
JP5 |
pins 1 & 2 closed |
|
BIOS type select 27256 |
JP5 |
pins 2 & 3 closed | |
|
|
NPU clock speed select 4.77MHz |
JP6 |
pins 1 & 2 closed |
|
NPU clock speed select 8MHz/10.77MHz |
JP6 |
pins 2 & 3 closed | |
|
|
Factory configured - do not alter |
JP7 |
Closed |
|
|
CPU clock speed select 12MHz |
JP10 |
Closed |
|
CPU clock speed select 12MHz |
JP10 |
Open | |
|
DRAM CONFIGURATION | ||||||
|
Size |
Bank 0 |
Parity 0 |
Bank 1 |
Parity 1 |
Bank Oa |
Bank 1a |
|
512KB |
(4) 44256 & |
(2) 41256 |
NONE |
NONE |
(2) 256K x 9 |
NONE |
|
1MB |
(4) 44256 & |
(2) 41256 |
(4) 44256 & |
(2) 41256 |
NONE |
NONE |
|
1MB |
NONE |
NONE |
NONE |
NONE |
(2) 256K x 9 |
(2) 256K x 9 |
|
2MB |
NONE |
NONE |
NONE |
NONE |
(2) 1M x 9 |
NONE |
|
2.5MB |
(4) 44256 & |
(2) 41256 |
NONE |
NONE |
(2) 1M x 9 |
(2) 1M x 9 |
|
2.5MB |
NONE |
NONE |
(4) 44256 & |
(2) 41256 |
(2) 1M x 9 |
(2) 1M x 9 |
|
4MB |
NONE |
NONE |
NONE |
NONE |
(2) 1M x 9 |
(2) 1M x 9 |