QUATECH, INC.
QS-2000/3000
|
Card Type |
Serial controller |
|
Chipset/Controller |
Unidentified UART |
|
I/O Options |
Serial I/O ports (2) |
|
Maximum DRAM |
N/A |
|
CONNECTIONS | |||
|
Purpose |
Location |
Purpose |
Location |
|
DB-37 I/O port |
CN1 |
6-pin RJ-11 I/O port |
CN2 |
|
CHANNEL 1 LOOPBACK CONFIGURATION | ||
|
Setting |
J1 | |
|
RTS/CTS loopback |
Pins 1 & 5 closed, 1 & 2 open | |
|
Transmit RTS |
Pins 5 & 6 closed, 6 & 7 open | |
|
Receive CTS |
Pins 1 & 2 closed, 2 & 3 open | |
|
RCLK/XCLK loopback |
Pins 3 & 7 closed, 2 & 3 open | |
|
Transmit XCLK |
Pins 6 & 7 closed, 5 & 6 open | |
|
Receive RCLK |
Pins 2 & 3 closed, 1 & 2 open | |
|
AUX OUT/AUX IN loopback |
Pins 2 & 6 closed, 5 & 6, 6 & 7 open | |
|
Half Duplex |
Pins 4 & 8 closed | |
|
Full Duplex |
Pins 4 & 8 open | |
|
CHANNEL 2 LOOPBACK CONFIGURATION | ||
|
Setting |
J2 | |
|
RTS/CTS loopback |
Pins 1 & 5 closed, 1 & 2 open | |
|
Transmit RTS |
Pins 5 & 6 closed, 6 & 7 open | |
|
Receive CTS |
Pins 1 & 2 closed, 2 & 3 open | |
|
RCLK/XCLK loopback |
Pins 3 & 7 closed, 2 & 3 open | |
|
Transmit XCLK |
Pins 6 & 7 closed, 5 & 6 open | |
|
Receive RCLK |
Pins 2 & 3 closed, 1 & 2 open | |
|
AUX OUT/AUX IN loopback |
Pins 2 & 6 closed, 5 & 6, 6 & 7 open | |
|
Half Duplex |
Pins 4 & 8 closed | |
|
Full Duplex |
Pins 4 & 8 open | |
|
CHANNEL 3 LOOPBACK CONFIGURATION | ||
|
Setting |
J3 | |
|
RTS/CTS loopback |
Pins 1 & 5 closed, 1 & 2 open | |
|
Transmit RTS |
Pins 5 & 6 closed, 6 & 7 open | |
|
Receive CTS |
Pins 1 & 2 closed, 2 & 3 open | |
|
RCLK/XCLK loopback |
Pins 3 & 7 closed, 2 & 3 open | |
|
Transmit XCLK |
Pins 6 & 7 closed, 5 & 6 open | |
|
Receive RCLK |
Pins 2 & 3 closed, 1 & 2 open | |
|
AUX OUT/AUX IN loopback |
Pins 2 & 6 closed, 5 & 6, 6 & 7 open | |
|
Half Duplex |
Pins 4 & 8 closed | |
|
Full Duplex |
Pins 4 & 8 open | |
|
CHANNEL 4 LOOPBACK CONFIGURATION | ||
|
Setting |
J4 | |
|
RTS/CTS loopback |
Pins 1 & 5 closed, 1 & 2 open | |
|
Transmit RTS |
Pins 5 & 6 closed, 6 & 7 open | |
|
Receive CTS |
Pins 1 & 2 closed, 2 & 3 open | |
|
RCLK/XCLK loopback |
Pins 3 & 7 closed, 2 & 3 open | |
|
Transmit XCLK |
Pins 6 & 7 closed, 5 & 6 open | |
|
Receive RCLK |
Pins 2 & 3 closed, 1 & 2 open | |
|
AUX OUT/AUX IN loopback |
Pins 2 & 6 closed, 5 & 6, 6 & 7 open | |
|
Half Duplex |
Pins 4 & 8 closed | |
|
Full Duplex |
Pins 4 & 8 open | |
|
INPUT CLOCK FREQUENCY | ||
|
MHz |
J5 | |
|
1.8432 |
Pins 1 & 2, 3 & 6, 4 & 5 closed | |
|
3.6864 |
Pins 2 & 3, 4 & 5 closed | |
|
9.216 |
Pins 1 & 2, 5 & 6 closed | |
|
18.432 |
Pins 2 & 5 closed | |